LAXP2-5E-5MN132E Lattice

LA-LatticeXP2 现场可编程门阵列

汽车电子 FPGA

5k LUTs 1.2V Automotive 132-Pin CSBGA

LAXP2-5E-5MN132E

LAXP2-5E-5MN132E之简介

LA-LatticeXP2 devices combine a Look-up Table (LUT) based FPGA fabric with non-volatile Flash cells in an architecture referred to as flexiFLASH.

The flexiFLASH approach provides benefits including instant-on, infinite reconfigurability, on chip storage with FlashBAK embedded block memory and Serial TAG memory and design security. The parts also support Live Update technology with TransFR, 128-bit AES Encryption and Dual-boot technologies.

The LA-LatticeXP2 FPGA fabric was optimized for the new technology from the outset with high performance and low cost in mind. LA-LatticeXP2 devices include LUT-based logic, distributed and embedded memory, Phase Locked Loops (PLLs), pre-engineered source synchronous I/O support and enhanced sysDSP blocks.

Lattice Diamond® design software allows large and complex designs to be efficiently implemented using the LALatticeXP2 family of FPGA devices. Synthesis library support for LA-LatticeXP2 is available for popular logic synthesis tools. The Diamond software uses the synthesis tool output along with the constraints from its floor planning tools to place and route the design in the LA-LatticeXP2 device. The Diamond design tool extracts the timing from the routing and back-annotates it into the design for timing verification.

Lattice provides many pre-designed Intellectual Property (IP) LatticeCORE™ modules for the LA-LatticeXP2 family. By using these IPs as standardized blocks, designers are free to concentrate on the unique aspects of their design, increasing their productivity

LAXP2-5E-5MN132E之规格

制造商: Lattice
产品种类: FPGA - 现场可编程门阵列
RoHS: YES
产品: XP2
逻辑元件数量: 5000
逻辑数组块数量——LAB: 625
输入/输出端数量: 86 I/O
工作电源电压: 1.2 V
最小工作温度: - 40 C
最大工作温度: + 125 C
安装风格: SMD/SMT
封装 / 箱体: CSBGA-132
封装: Tray
高度: 1.1 mm (Max)
长度: 8 mm
系列: LAXP2-5E-5MN
宽度: 8 mm
商标: Lattice
分布式RAM: 10 kbit
内嵌式块RAM - EBR: 166 kbit
湿度敏感性: Yes
产品类型: FPGA - Field Programmable Gate Array
工厂包装数量: 360
子类别: Programmable Logic ICs
电源电压-最大: 1.26 V
电源电压-最小: 1.14 V
总内存: 176 kbit

LAXP2-5E-5MN132E之架构总览

Each LA-LatticeXP2 device contains an array of logic blocks surrounded by Programmable I/O Cells (PIC). Interspersed between the rows of logic blocks are rows of sysMEM™ Embedded Block RAM (EBR) and a row of sysDSP™ Digital Signal Processing blocks as shown in Figure 2-1.

On the left and right sides of the Programmable Functional Unit (PFU) array, there are Non-volatile Memory Blocks. In configuration mode the nonvolatile memory is programmed via the IEEE 1149.1 TAP port or the sysCONFIG™ peripheral port. On power up, the configuration data is transferred from the Non-volatile Memory Blocks to the configuration SRAM. With this technology, expensive external configuration memory is not required, and designs are secured from unauthorized read-back. This transfer of data from non-volatile memory to configuration SRAM via wide busses happens in microseconds, providing an “instant-on” capability that allows easy interfacing in many applications. LA-LatticeXP2 devices can also transfer data from the sysMEM EBR blocks to the Non-volatile Memory Blocks at user request.

There are two kinds of logic blocks, the PFU and the PFU without RAM (PFF). The PFU contains the building blocks for logic, arithmetic, RAM and ROM functions. The PFF block contains building blocks for logic, arithmetic and ROM functions. Both PFU and PFF blocks are optimized for flexibility allowing complex designs to be implemented quickly and efficiently. Logic Blocks are arranged in a two-dimensional array. Only one type of block is used per row.

LA-LatticeXP2 devices contain one or more rows of sysMEM EBR blocks. sysMEM EBRs are large dedicated 18 kbit memory blocks. Each sysMEM block can be configured in a variety of depths and widths of RAM or ROM. In addition, LA-LatticeXP2 devices contain up to two rows of DSP Blocks. Each DSP block has multipliers and adder/accumulators, which are the building blocks for complex signal processing capabilities.

Each PIC block encompasses two PIOs (PIO pairs) with their respective sysIO buffers. The sysIO buffers of the LALatticeXP2 devices are arranged into eight banks, allowing the implementation of a wide variety of I/O standards. PIO pairs on the left and right edges of the device can be configured as LVDS transmit/receive pairs. The PIC logic also includes pre-engineered support to aid in the implementation of high speed source synchronous standards such as 7:1 LVDS interfaces, found in many display applications, and memory interfaces including DDR and DDR2.

Other blocks provided include PLLs and configuration functions. The LA-LatticeXP2 architecture provides up to four General Purpose PLLs (GPLL) per device. The GPLL blocks are located in the corners of the device.

The configuration block that supports features such as configuration bit-stream de-encryption, transparent updates and dual boot support is located between banks two and three. Every device in the LA-LatticeXP2 family supports a sysCONFIG port, muxed with bank seven I/Os, which supports serial device configuration. A JTAG port is provided between banks two and three.

This family also provides an on-chip oscillator. LA-LatticeXP2 devices use 1.2 V as their core voltage.

LAXP2-5E-5MN132E之特性

flexiFLASH™ Architecture

• Instant-on

• Infinitely reconfigurable

• Single chip • FlashBAK™ technology

• Serial TAG memory

• Design security

AEC-Q100 Tested and Qualified

Live Update Technology

• TransFR™ technology

• Secure updates with 128 bit AES encryption

• Dual-boot with external SPI

sysDSP™ Block

• Three to five blocks for high performance Multiply and Accumulate

• 12 to 20 18 x 18 multipliers

• Each block supports one 36 x 36 multiplier or four 18 x 18 or eight 9 x 9 multipliers

Embedded and Distributed Memory

• Up to 276 kbits sysMEM™ EBR

• Up to 35 kbits Distributed RAM

sysCLOCK™ PLLs

• Up to four analog PLLs per device

• Clock multiply, divide and phase shifting

Flexible I/O Buffer

• sysIO™ buffer supports:

– LVCMOS 33/25/18/15/12; LVTTL

– SSTL 33/25/18 class I, II

– HSTL15 class I; HSTL18 class I, II

– PCI

– LVDS, Bus-LVDS, MLVDS, LVPECL, RSDS

Pre-engineered Source Synchronous Interfaces

• DDR / DDR2 interfaces up to 200 MHz

• 7:1 LVDS interfaces support display applications

• XGMII

Density And Package Options

• 5k to 17k LUT4s, 86 to 358 I/Os

• csBGA, ftBGA, TQFP and PQFP packages

• Density migration supported

Flexible Device Configuration

• SPI (master and slave) Boot Flash Interface

• Dual Boot Image supported

• Soft Error Detect (SED) macro embedded

System Level Support

• IEEE 1149.1 and IEEE 1532 Compliant

• On-chip oscillator for initialization & general use

• Devices operate with 1.2 V power supply

LAXP2-5E-5MN132E之Datasheet数据表:下载
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